1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device of an SIP (System In a Package) using semiconductor integrated circuit chips with I/F (Interface) functions added thereto.
2. Description of the Prior Art
FIG. 18 is a plan view showing a semiconductor integrated circuit device (related art example 1) of a conventional SIP (System In a Package). In the drawing, reference numeral 10 indicates a bonding pad (bonding PAD), reference numeral 20 indicates a semiconductor integrated circuit chip A (Chip A) disposed on the bonding PAD 10, and reference numeral 35 indicates a semiconductor integrated circuit chip B (Chip B) excluding I/F functions, which is disposed on the bonding PAD 10, respectively. Reference numerals 40a–40e and 43a–43e respectively indicate pads (PADs) of the Chip A20, and reference numerals 41a–41e and 42a–42d respectively indicate pads (PADs) of the Chip B35. Reference numerals 50a–50f and 51a–51i respectively indicate connecting leads (LEADs) disposed around the bonding PAD 10. Reference numerals 60b, 60d and 60e respectively indicate bonding wires for connecting the Chip A20 and the Chip b35 or LEADs 50a–50f. Reference numerals 62a, 62b, 62d and 62f respectively indicate bonding wires for connecting the Chip A20 and the LEADs 51a–51i. Reference numerals 61a–61d respectively indicate bonding wires for connecting the Chip B35 and the LEADs 50a–50f. 
The operation of the semiconductor integrated circuit device will next be described.
The bonding wires 62b and 62d respectively connect the PADs 43a and 43b of the Chip A20 to the LEADs 51b and 51d. The bonding wires 61a, 61b, 61c and 61d respectively connect the PADs 42a, 42b, 42c and 42d of the Chip B35 to the LEADs 50a, 50c, 50d and 50e. The bonding wire 60d connects the PAD 40d of the Chip A20 to the PAD 41d of the Chip B35. Since these bonding wires 62b, 62d, 61a, 61b, 61c, 61d and 60d are those for connecting between the adjacent PADs and LEADs or between the adjacent PADs, they are not wired so as to straddle the Chip A20 or the Chip B35.
On the other hand, the bonding wires 60b and 60e respectively connect the PADs 40b and 40e of the Chip A20 to the LEADs 50b and 50f, and the bonding wires 62a and 62f respectively connect the PADs 40a and 40c of the Chip A20 to the LEADs 51a and 51f. Since these bonding wires 60b, 60e, 62a and 62f are those for connecting between non-adjacent PADs and LEADs, they are wired so as to extend across the Chip A20 or Chip B35.
FIG. 19 is a plan view showing a semiconductor integrated circuit device (related art example 2) of a conventional SIP (System In a Package). In the drawing, reference numeral 16 indicates a bonding PAD, reference numeral 253 indicates a Chip A disposed on the bonding PAD16, and reference numeral 254 indicates a Chip B disposed on the bonding PAD 16, respectively. Reference numerals 311a–311h and 311p indicate PADs of the Chip A253, and reference numerals 312i and 312j indicate PADs of the Chip B254, respectively. Reference numerals 321a, 321c, 321e, 321g, 321i and 321j respectively indicate signal LEADs disposed around the bonding PAD 16, and reference numerals 322b, 322d, 322f, 322h and 322p respectively indicate power LEADs. Reference numerals 361a and 361b indicate bonding PAD fixing LEADs respectively. Reference numerals 352a–352h, 353i and 353j indicate bonding wires respectively.
The operation of the semiconductor integrated circuit device will next be explained.
The signal LEADs321a, 321c, 321e, 321g, 321i and 321j are respectively connected to the PADs 311a, 311c, 311e and 311g of the Chip A253 and the PADs312i and 312j of the Chip B254 by the bonding wires 352a, 352c, 352e, 352g, 353i and 353j. The power LEADs 322b, 322d, 322f, 322h and 322p are respectively connected to the PADs 311b, 311d, 311f, 311h and 311p of the Chip A253 by the bonding wires 352b, 352d, 352f, 352h and 352p. The bonding PAD 16 is fixed by the bonding PAD fixing LEADs301a and 361b. 
Since the PADs 311b, 311d, 311f, 311h and 311p are connected to their corresponding power LEADs 322b, 322d, 322f, 322h and 322p and supplied with power, the power LEADs identical in number to the PADs supplied with the power are provided.
There arises a drawback in that-since the conventional semiconductor integrated circuit device is constructed as described above, a further reduction in chip size where a plurality of chips are mounted, will cause a difficulty in connecting bonding wires between PADs of a chip and LEADs at positions where the PADs of the chip and the LEADs do not adjoin, when the number of the bonding wires is identical or increases, thereby interfering with the reduction in chip size.
There also arises a drawback in that a further reduction in chip size where a plurality of chips are mounted, will cause a difficulty in supplying stable power at positions where PADs of a chip and LEADs do not adjoin, when the number of bonding wires is identical or increases, thereby interfering with the reduction in chip size.
Further, there arises a drawback in that since a plurality of chips are disposed adjacent to one another, the influence of temperatures on the respective chips by heat generation of the chips cannot be avoided, and when a chip size is further reduced, the condition of a chip-in temperature distribution must be confirmed from the need for taking into consideration the above influence of temperatures on the respective chips.